SonicWall is a cybersecurity forerunner with more than 30 years of expertise and is recognized as a leading partner-first company, ensuring our partners and their customers are never alone in the fight against cybercrime. With the ability to build, scale and manage security across the cloud, hybrid and traditional environments in real-time, SonicWall provides relentless security against the most evasive cyberattacks across endless exposure points for increasingly remote, mobile and cloud-enabled users. With its own threat research center, SonicWall can quickly and economically provide purpose-built security solutions to enable any organization—enterprise, government agencies and SMBs—around the world. For more information, visit www.sonicwall.com or follow us on Twitter, LinkedIn, Facebook and Instagram.

About the Role

SonicWall is seeking a Software Dev Senior Engineer (Dataplane) with deep expertise in High Availability, Fast-Path Packet Processing, and Distributed Systems to architect and optimize the dataplane HA subsystem across SonicWall NGFW hardware and virtual firewalls — driving sub-millisecond session state synchronization, zero-packet-loss failover, and line-rate forwarding for IPsec, SSL-VPN, and TCP/UDP flows at 10G–100G+.

Responsibilities

Dataplane HA Architecture — Own fast-path HA engine design covering Active/Standby mirroring, Active/Active flow redistribution, and zero-drop VMAC/VIP failover.
Stateful Session Mirroring — Build low-overhead dataplane sync for TCP/UDP 5-tuple tables, IPsec SA fast-path, SSL-VPN contexts, and L7 states across HA peers at line rate.
Lock-Free Session Tables — Design NUMA-aware, lock-free (RCU/CAS/seqlock) session tables for multi-core pipelines sustaining tens of millions of concurrent sessions at sub-microsecond latency.
High-Performance Sync Fabric — Engineer zero-copy ring buffer / DPDK mempool-based sync with prioritized queuing for IPsec/SSL-VPN state at sub-millisecond replication latency.
Asymmetric Flow Handling — Implement cross-node packet redirect, flow pinning, and state sync for asymmetric TCP/UDP and IPsec traffic in Active/Active topologies.
Hardware Offload Integration — Mirror offloaded SA/session state across HA peers for inline crypto engines (QAT, OCTEON, Nitrox) to preserve hardware acceleration post-failover.
Hitless Failover & ISSU — Ensure zero packet drops, zero IPsec renegotiations, and zero TCP resets during failover and In-Service Software Upgrades.
Technical Leadership — Drive dataplane HA architecture reviews, define benchmarks, author Specs, and mentor senior dataplane engineers.

Requirements

7+ years of C/C++ development for high-performance networking dataplanes — firewalls, routers, switches, or carrier-grade appliances.
Dataplane HA & Fast-Path — Production experience with lock-free session mirroring, Active/Active packet steering, and stateful failover at 10G–100G+ line rates.
Packet Processing Frameworks — Deep hands-on with DPDK, ODP, OFP, or XDP/eBPF including zero-copy buffers, ring queues, and CPU core pinning.
Protocol Fast-Path — Expertise in IPsec SA fast-path lookups, SSL-VPN encapsulation/decapsulation, and TCP/UDP conntrack state synchronization.
Hardware Acceleration — Working knowledge of crypto offload engines (QAT, Marvell OCTEON, Cavium/Nitrox) or SmartNIC/DPU integration into packet pipelines.
Multi-Core & NUMA — Expert in cache-line alignment, lock-free concurrency, memory barriers, and NUMA-aware data structures for packet processors.
Debugging — Proficient with perf, GDB, ftrace, eBPF, tcpdump, and Wireshark for diagnosing dataplane race conditions and session continuity failures.

Nice to Have

Experience with NGFW dataplane HA (Palo Alto PAN-OS, Fortinet FortiOS, Cisco ASA/FTD, Check Point ClusterXL).
Cloud/virtual firewall dataplane HA (AWS SR-IOV, Azure Accelerated Networking, VMware ESXi DVS).
Exposure to 400GbE, SmartNIC, or DPU architectures (NVIDIA BlueField, Intel IPU).
Automated failure-injection and packet-level testing (IXIA, Spirent, TRex).

About the Role

SonicWall is seeking a Principal Engineer (Dataplane) with deep expertise in High Availability, Fast-Path Packet Processing, and Distributed Systems to architect and optimize the dataplane HA subsystem across SonicWall NGFW hardware and virtual firewalls — driving sub-millisecond session state synchronization, zero-packet-loss failover, and line-rate forwarding for IPsec, SSL-VPN, and TCP/UDP flows at 10G–100G+.

Responsibilities

Dataplane HA Architecture — Own fast-path HA engine design covering Active/Standby mirroring, Active/Active flow redistribution, and zero-drop VMAC/VIP failover.
Stateful Session Mirroring — Build low-overhead dataplane sync for TCP/UDP 5-tuple tables, IPsec SA fast-path, SSL-VPN contexts, and L7 states across HA peers at line rate.
Lock-Free Session Tables — Design NUMA-aware, lock-free (RCU/CAS/seqlock) session tables for multi-core pipelines sustaining tens of millions of concurrent sessions at sub-microsecond latency.
High-Performance Sync Fabric — Engineer zero-copy ring buffer / DPDK mempool-based sync with prioritized queuing for IPsec/SSL-VPN state at sub-millisecond replication latency.
Asymmetric Flow Handling — Implement cross-node packet redirect, flow pinning, and state sync for asymmetric TCP/UDP and IPsec traffic in Active/Active topologies.
Hardware Offload Integration — Mirror offloaded SA/session state across HA peers for inline crypto engines (QAT, OCTEON, Nitrox) to preserve hardware acceleration post-failover.
Hitless Failover & ISSU — Ensure zero packet drops, zero IPsec renegotiations, and zero TCP resets during failover and In-Service Software Upgrades.
Technical Leadership — Drive dataplane HA architecture reviews, define benchmarks, author Specs, and mentor senior dataplane engineers.

Requirements

7+ years of C/C++ development for high-performance networking dataplanes — firewalls, routers, switches, or carrier-grade appliances.
Dataplane HA & Fast-Path — Production experience with lock-free session mirroring, Active/Active packet steering, and stateful failover at 10G–100G+ line rates.
Packet Processing Frameworks — Deep hands-on with DPDK, ODP, OFP, or XDP/eBPF including zero-copy buffers, ring queues, and CPU core pinning.
Protocol Fast-Path — Expertise in IPsec SA fast-path lookups, SSL-VPN encapsulation/decapsulation, and TCP/UDP conntrack state synchronization.
Hardware Acceleration — Working knowledge of crypto offload engines (QAT, Marvell OCTEON, Cavium/Nitrox) or SmartNIC/DPU integration into packet pipelines.
Multi-Core & NUMA — Expert in cache-line alignment, lock-free concurrency, memory barriers, and NUMA-aware data structures for packet processors.
Debugging — Proficient with perf, GDB, ftrace, eBPF, tcpdump, and Wireshark for diagnosing dataplane race conditions and session continuity failures.

Nice to Have

Experience with NGFW dataplane HA (Palo Alto PAN-OS, Fortinet FortiOS, Cisco ASA/FTD, Check Point ClusterXL).
Cloud/virtual firewall dataplane HA (AWS SR-IOV, Azure Accelerated Networking, VMware ESXi DVS).
Exposure to 400GbE, SmartNIC, or DPU architectures (NVIDIA BlueField, Intel IPU).
Automated failure-injection and packet-level testing (IXIA, Spirent, TRex).

#LI-DS9

#LI-Pune

#LI-HighAvailability

#LI-DPDK

SonicWall is an equal opportunity employer.

We are committed to creating a diverse environment and are an equal opportunity employer. All qualified applicants receive consideration for employment without regard to race, color, ethnicity, religion, sex, gender, gender identity and expression, sexual orientation, national origin, disability, age, marital status, veteran status, pregnancy, or any other basis prohibited by applicable law.

At SonicWall, we pride ourselves on recruiting a diverse mix of talented people and providing active security solutions in 100+ countries.

Applicant Privacy Notice

About the Role

Responsibilities

Dataplane HA Architecture — Own fast-path HA engine design covering Active/Standby mirroring, Active/Active flow redistribution, and zero-drop VMAC/VIP failover.
Stateful Session Mirroring — Build low-overhead dataplane sync for TCP/UDP 5-tuple tables, IPsec SA fast-path, SSL-VPN contexts, and L7 states across HA peers at line rate.
Lock-Free Session Tables — Design NUMA-aware, lock-free (RCU/CAS/seqlock) session tables for multi-core pipelines sustaining tens of millions of concurrent sessions at sub-microsecond latency.
High-Performance Sync Fabric — Engineer zero-copy ring buffer / DPDK mempool-based sync with prioritized queuing for IPsec/SSL-VPN state at sub-millisecond replication latency.
Asymmetric Flow Handling — Implement cross-node packet redirect, flow pinning, and state sync for asymmetric TCP/UDP and IPsec traffic in Active/Active topologies.
Hardware Offload Integration — Mirror offloaded SA/session state across HA peers for inline crypto engines (QAT, OCTEON, Nitrox) to preserve hardware acceleration post-failover.
Hitless Failover & ISSU — Ensure zero packet drops, zero IPsec renegotiations, and zero TCP resets during failover and In-Service Software Upgrades.
Technical Leadership — Drive dataplane HA architecture reviews, define benchmarks, author Specs, and mentor senior dataplane engineers.

Requirements

7+ years of C/C++ development for high-performance networking dataplanes — firewalls, routers, switches, or carrier-grade appliances.
Dataplane HA & Fast-Path — Production experience with lock-free session mirroring, Active/Active packet steering, and stateful failover at 10G–100G+ line rates.
Packet Processing Frameworks — Deep hands-on with DPDK, ODP, OFP, or XDP/eBPF including zero-copy buffers, ring queues, and CPU core pinning.
Protocol Fast-Path — Expertise in IPsec SA fast-path lookups, SSL-VPN encapsulation/decapsulation, and TCP/UDP conntrack state synchronization.
Hardware Acceleration — Working knowledge of crypto offload engines (QAT, Marvell OCTEON, Cavium/Nitrox) or SmartNIC/DPU integration into packet pipelines.
Multi-Core & NUMA — Expert in cache-line alignment, lock-free concurrency, memory barriers, and NUMA-aware data structures for packet processors.
Debugging — Proficient with perf, GDB, ftrace, eBPF, tcpdump, and Wireshark for diagnosing dataplane race conditions and session continuity failures.

Nice to Have

Experience with NGFW dataplane HA (Palo Alto PAN-OS, Fortinet FortiOS, Cisco ASA/FTD, Check Point ClusterXL).
Cloud/virtual firewall dataplane HA (AWS SR-IOV, Azure Accelerated Networking, VMware ESXi DVS).
Exposure to 400GbE, SmartNIC, or DPU architectures (NVIDIA BlueField, Intel IPU).
Automated failure-injection and packet-level testing (IXIA, Spirent, TRex).

About the Role

Responsibilities

Dataplane HA Architecture — Own fast-path HA engine design covering Active/Standby mirroring, Active/Active flow redistribution, and zero-drop VMAC/VIP failover.
Stateful Session Mirroring — Build low-overhead dataplane sync for TCP/UDP 5-tuple tables, IPsec SA fast-path, SSL-VPN contexts, and L7 states across HA peers at line rate.
Lock-Free Session Tables — Design NUMA-aware, lock-free (RCU/CAS/seqlock) session tables for multi-core pipelines sustaining tens of millions of concurrent sessions at sub-microsecond latency.
High-Performance Sync Fabric — Engineer zero-copy ring buffer / DPDK mempool-based sync with prioritized queuing for IPsec/SSL-VPN state at sub-millisecond replication latency.
Asymmetric Flow Handling — Implement cross-node packet redirect, flow pinning, and state sync for asymmetric TCP/UDP and IPsec traffic in Active/Active topologies.
Hardware Offload Integration — Mirror offloaded SA/session state across HA peers for inline crypto engines (QAT, OCTEON, Nitrox) to preserve hardware acceleration post-failover.
Hitless Failover & ISSU — Ensure zero packet drops, zero IPsec renegotiations, and zero TCP resets during failover and In-Service Software Upgrades.
Technical Leadership — Drive dataplane HA architecture reviews, define benchmarks, author Specs, and mentor senior dataplane engineers.

Requirements

7+ years of C/C++ development for high-performance networking dataplanes — firewalls, routers, switches, or carrier-grade appliances.
Dataplane HA & Fast-Path — Production experience with lock-free session mirroring, Active/Active packet steering, and stateful failover at 10G–100G+ line rates.
Packet Processing Frameworks — Deep hands-on with DPDK, ODP, OFP, or XDP/eBPF including zero-copy buffers, ring queues, and CPU core pinning.
Protocol Fast-Path — Expertise in IPsec SA fast-path lookups, SSL-VPN encapsulation/decapsulation, and TCP/UDP conntrack state synchronization.
Hardware Acceleration — Working knowledge of crypto offload engines (QAT, Marvell OCTEON, Cavium/Nitrox) or SmartNIC/DPU integration into packet pipelines.
Multi-Core & NUMA — Expert in cache-line alignment, lock-free concurrency, memory barriers, and NUMA-aware data structures for packet processors.
Debugging — Proficient with perf, GDB, ftrace, eBPF, tcpdump, and Wireshark for diagnosing dataplane race conditions and session continuity failures.

Nice to Have

Experience with NGFW dataplane HA (Palo Alto PAN-OS, Fortinet FortiOS, Cisco ASA/FTD, Check Point ClusterXL).
Cloud/virtual firewall dataplane HA (AWS SR-IOV, Azure Accelerated Networking, VMware ESXi DVS).
Exposure to 400GbE, SmartNIC, or DPU architectures (NVIDIA BlueField, Intel IPU).
Automated failure-injection and packet-level testing (IXIA, Spirent, TRex).

#LI-DS9

#LI-Pune

#LI-HighAvailability

#LI-DPDK

SonicWall is an equal opportunity employer.

Applicant Privacy Notice

Senior Software Engineer - Dataplane High Availability & Clustering

What we know about this role

Skills required

Job description

Get tomorrow's jobs before you have to search

Someone shared one job with you. ASAI keeps finding the rest.

Senior Software Engineer - Dataplane High Availability & Clustering

What we know about this role

Skills required

Job description

Get tomorrow's jobs before you have to search

Someone shared one job with you. ASAI keeps finding the rest.